1. Field of the Invention
The present invention relates to an apparatus and a method for controlling the phase of a sampling clock signal in a liquid crystal display (hereinafter, referred to as LCD) system, and more particularly, to an apparatus and a method for controlling the phase of a sampling clock signal to accurately adjust the state of a screen.
2. Description of the Related Art
An LCD system is a kind of flat panel display. Such LCD systems have a function of converting a received analog image signal into a digital image signal before the image is scaled to a displayable format so that the LCD systems can be applied to an analog image processing environment.
However, the quality of a screen is deteriorated if the phase of a sampling clock signal used for converting the analog image signal to the digital image signal is out of phase with the received analog image signal. Thus, whenever the received analog signal is changed, the phase of the sampling clock signal must be adjusted so that the phase of the sampling clock signal corresponds with the phase of the received analog image signal.
To do this, it has been proposed that LCD systems detect level difference values between image signals, which are sampled by delaying the phase of the sampling clock signal several times, and then detects an optimum phase point for the sampling clock signal utilizing the detected level difference values. Also, the sampling clock signal having the optimum phase point is used for converting the analog image signal to the digital image signal.
A method for controlling the phase of the sampling clock signal in the proposed LCD system will be described in more detail with reference to FIG. 1. When an analog image signal is applied as shown in (a) of FIG. 1, two points of the analog image signal are sampled utilizing a sampling clock signal having a phase shown in (b) of FIG. 1. Next, a level difference value Vd1 between the two points of the analog image signal is detected. As shown in (c) of FIG. 1, two points of an analog image signal input are sampled utilizing a sampling clock signal having a phase which is delayed by t1. Next, a level difference value Vd2 between the two points of the analog image signal is detected. As shown in (d) of FIG. 1, two points of an analog image signal input are sampled utilizing a sampling clock signal having a phase which is delayed by t2. Next, a level difference value Vd3 between the two points of the analog image signal is detected.
The detected level difference values Vd1, Vd2, and Vd3 are compared with each other to detect the maximum level difference value. The phase of a sampling clock signal is controlled in a way that the sampling clock signal, which is used for detecting the maximum level difference value, is used for converting an analog image signal to a digital image signal. The sampling clock signal used for detecting the maximum level difference value is determined to be a sampling clock signal having an optimum phase, since the sampling clock signal is regarded as detecting a peak point of an input image signal.
A level difference between two points of an input image signal is the maximum value, i.e., a peak point of the image signal, as described above. However, in reality, the two points of the sampled image signal may only be adjacent to the peak point of the sampled image signal. If the two points of the sampled image signal are adjacent to the peak point instead of at the peak point, a screen may not be accurately adjusted using the sampling clock signal.